Automotive-grade high-performance autonomous driving chip

1、Application scalability, autonomous driving chip optimized for AD/ADAS design:

1、Application scalability, autonomous driving chip optimized for AD/ADAS design:

The architecture can simultaneously support L2+ and above autonomous driving applications.

Rich IO interfaces enable multi-chip cascading expansion.


2、Multi-sensor interface support, high-performance ISP:

Seamless access to multi-sensors such as cameras, LiDAR, and millimeter-wave radars.

High-performance NeuralIQ ISP technology supporting real-time processing of up to 16 channels of high-definition and high-dynamic range (HDR) images.

1.2Gpps high-dynamic image processing capability.

Built-in high-performance computer vision (CV) acceleration engine and 4K video codec engine.


3、High computing power, high energy efficiency ratio, multi-dimensional heterogeneous architecture algorithms and CV acceleration engine:

Up to 58 TOPS (INT8) acceleration engine.

Symmetric multi-core, high-performance DSP, and CV acceleration cores.

Ultra-high-performance 8-core ARM Cortex A55 Processor @ 1.5GHz.

4、Architecture, processes, design, and certification for driving safety:

AEC-Q100 Grade 2, ISO 26262 ASIL-B compliance.

Integrated independent functional safety and information security islands.

Support for automotive-grade 64-bit LPDDR4.

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